low-level / hardware-focused software engineer
Tools Team, Antmicro · Wrocław, Poland
I work close to the boundary between software and hardware: Verilator tooling, performance-sensitive C++, FPGA and digital design flows, CUDA kernels, Linux systems, and practical hardware debugging.
$ ./artur --focus Verilator, FPGA, CUDA, Linux systems
$ git log -1 fix simulator edge cases without giving up performance
$ grep debug work.log debug hardware, measure bottlenecks, verify behavior
current work
My work is centered on low-level tooling, simulation behavior, and workflows where small correctness or performance mistakes have a large blast radius.
Developing C++ tooling around Verilator and topwrap for digital design, simulation, and verification workflows.
Hands-on diagnostics, repair, stability testing, and custom system building for PCs, servers, GPUs, RAM, and Linux-based setups.
selected work
A small set of work that reflects the same pattern: understand the system, find the bottleneck, and make the implementation match the hardware.
CUDA-based SHA3x hasher reaching 700 MH/s on an RTX 4070 Super by tuning kernel structure and memory access patterns for throughput.
FPGA implementation of a SHA3x hasher achieving 33 MH/s on a DE1-SoC, using a multicycle design to reduce critical path pressure.
TCP/UDP proxy for real-time packet inspection and modification, with binary protocol reverse engineering and live application-layer payload manipulation.
Built a low-cost distributed compute cluster from more than 80 smartphones with 8-core ARM CPUs, Linux tooling, and custom maintenance workflows.
open source
Public GitHub activity reflects a current emphasis on Verilator internals, simulation correctness, and practical tooling.
Recent merged work includes fixes around property expression literal width, virtual interface method scheduling, and assign/deassign behavior.
Thesis work on implementing full force/release support in Verilator, connecting language semantics, simulator design, and runtime performance. Relevant links: thesis repository, verilator/verilator#7391.
Public CUDA mining implementation and performance-oriented hashing work, archived after the core experiment was completed.
Public writeups from Break The Syntax 2026, showing applied debugging, exploit reasoning, and careful technical communication.
toolbox
The useful overlap: systems programming, digital design, hardware debugging, and enough infrastructure work to keep the whole path observable.
education
Planned thesis topic: reducing DRAM refresh rates by identifying and mitigating leaky cells.
Completed in 2.5 years with grade 4.31/5.0. Thesis: implementing full support for force/release in Verilator.